The present invention generally relates to a computer system, and more particularly to a computer system having a direct memory access (DMA) mode.
Description of the Related Art Currently, to minimize power consumption, a DMA mode is used by a computer system. When the DMA mode is operating, a central processing unit (CPU) of the computer system is idle during transmission of data (e.g., sending data or receiving data).
FIG. 1 illustrates a conventional computer system disclosed in Japanese Patent Application Laid-Open No. 2-244312. A central processing unit (CPU) 101 is connected to a memory 102, and a plurality of peripheral circuits (e.g., a CPU clock control circuit 103, an interrupt control circuit 104, a DMA circuit 106, and a serial communication circuit 107) by a bus 111.
The CPU clock control circuit 103 controls a quartz oscillator 112, and outputs clock signals generated by the quartz oscillator 112 to the CPU 101 using a line k. In the DMA mode, the CPU clock control circuit 103 terminates an operation of the quartz oscillator 112, and therefore, the CPU 101 cannot process any instructions. During this time, the CPU does not consume electric power (e.g., current, voltage), and thus system power consumption is minimized.
When the DMA mode is finished, the CPU clock control circuit 103 starts the quartz oscillator 112 for generating clock signals. After obtaining a stable frequency for the clock signals (e.g., after a predetermined time), the CPU clock control circuit 103 supplies the clock signals to the CPU.
Thus, the DMA mode is accomplished. For brevity, a detailed explanation is not provided herein, because such is disclosed in the Japanese Patent Application Laid-Open No. 2-244312.
However, the CPU 101 of the conventional computer system cannot access readily and efficiently the memory 102, even if a high performance CPU (e.g., a reduced instruction set computer (RISC)--type CPU) is used as the CPU 101. Specifically, the CPU 101 and the memory 102 are connected together by the bus 111 connected commonly to the peripheral circuits. The bus 111 includes load capacities such as wiring capacities and input capacities from the peripheral circuits, thereby reducing the CPU's access speed to the memory.
Additionally, the bus 111 multiplexes addresses and data to reduce the wiring area on a semiconductor chip including the conventional computer system. Therefore, the CPU 101 requires several clocks (e.g., clock periods) to access the memory 102 due to the multiplexing operation.
Further, there is a delay time from finishing the DMA mode to generating a stable frequency for the clock signals because the quartz oscillator 112 is inoperable during the DMA mode. Normally, several milli-seconds are required to stabilize the oscillations of a quartz oscillator after it is started from an idle state.
As a result, the memory system cannot operate and process instructions with high-speed, especially after the quartz oscillator has been idle. This is a problem.